1. Field of the Invention
The present invention relates generally to the transmission of digital signals and more particularly to an improved technique for eliminating the effect of DC offset voltages in digital receivers particularly in nonwireline systems.
2. Description of the Prior Art
In digital communications, digitally modulated signals are demodulated usually by sampling the baseband signal at the baud interval and by comparing the sampled level with predetermined coded amplitude levels. In all such systems it is necessary to first eliminate any dc offset component in the baseband signal to be detected. Otherwise the zero level of the signal will be elevated (either +or -) and the detector will detect false levels because of the added dc voltage to the baseband signal. This translates into errors in the recovered data. By blocking the dc offset component, or restoring the true zero level to the baseband signal, the dfferential between the detector reference level and the zero signal level is eliminated.
In nonwire line systems, i.e. wireless transmission, restoring the true reference level is particularly important. And in an environment of multipoint digital communications, a digital receiver has to repeatedly switch between different transmitters to receive different signals from a number of various signal paths. With each different digital signal, a new dc offset level has to be established or the dc offset has to be blocked in each signal received. A digital transmitter can easily introduce an undesired frequency shift which translates as an added dc component in the demodulator in a frequency modulated system. It is very important to reset the dc reference level with each new transmitter as quickly as possible.
The traditional way that this problem is handled is through the use of series blocking capacitors in the receiver to block the dc component in the received data signal (provided the data itself is randomized and does not have any dc component). It is a cheap and fairly effective technique particularly for low speed data rates. To be effective the capacitor has to be fairly large so that the cutoff frequency is low. Unfortunately the larger the value of capacitance, the longer it takes to charge and discharge the device, which must be done every time a new signal enters a receiver or is powered up initially. Blocking capacitors typically take from 10 to 100 ms to charge, and in this amount of time significant amounts of data can be lost particularly for high speed data rates. Another problem encountered with simple blocking capacitors is caused by the apparent dc shift in the average data level which the data itself exhibits when particular strings of data occur, e.g. a long string of 1's. In multilevel data systems the data streams typically exhibit an apparent short-term dc component that shifts with the content of the data. When this occurs the blocking capacitor will shift the reference dc level which causes errors in the data receiver/decoder.
This invention is directed to an improved technique for eliminating the deleterious effect of dc offset voltages in digital receivers/decoders.